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1 ltc1282 s f ea t u re d u escriptio the ltc ? 1282 is a 6 m s, 140ksps, sampling 12-bit a/d converter that draws only 12mw from a single 3v or dual 3v supply. this easy-to-use device comes complete with 1.14 m s sample-and-hold, precision reference and inter- nally trimmed clock. unipolar and bipolar conversion modes provide flexibility for various applications. they are built with ltbicmos tm switched capacitor technology. the ltc1282 has a 25ppm/ c (max) internal reference and converts 0v to 2.5v unipolar inputs from a single 3v supply. with 3v supplies its input range is 1.25v with twos complement output format. maximum dc specifica- tions include 0.5lsb inl, 0.75lsb dnl and 25ppm/ c full-scale drift over temperature. outstanding ac perfor- mance includes 69db s/(n + d) and 77db thd at the nyquist input frequency of 70khz. the internal clock is trimmed for 6 m s maximum conver- sion time. the clock automatically synchronizes to each sample command eliminating problems with asynchro- nous clock noise found in competitive devices. a high speed parallel interface eases connections to fifos, dsps and microprocessors. 3v 140ksps 12-bit sampling a/d converter with reference n single supply 3v or 3v operation n 140ksps throughput rate n 12mw (typ) power dissipation n on-chip 25ppm/ c reference n internal synchronized clock; no clock required n high impedance analog input n 69db s/(n + d) and 77db thd at nyquist n 0.5lsb inl and 0.75lsb dnl max (a grade) n 2.7v guaranteed minimum supply voltage n esd protected on all pins n 24-pin narrow pdip and sw packages n 0v to 2.5v or 1.25v input ranges u s a o pp l ic at i n 3v powered systems n high speed data acquisition n digital signal processing n multiplexed data acquisition systems n audio and telecom processing n spectrum analysis input frequency (hz) 1k 0 enobs (effective number of bits) 3 5 7 10 10k ltc1282 ?ta02 1 4 6 9 12 11 8 2 100k 62 56 74 68 50 s/(n + d) (db) f sample = 140khz nyquist frequency effective bits and signal-to-(noise + distortion) vs input frequency , ltc and lt are registered trademarks of linear technology corporation. ltbicmos is a trademark of linear technology corporation 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd v dd v ss busy cs rd hben nc nc d0/8 d1/9 d2/10 d3/11 ltc1282 + 0.1 m f 10 m f 1.20v v ref output analog input (0v to 2.5v) + 10 m f 0.1 m f 3v 8- or 12-bit parallel bus m p control lines 1282 ta01 single 3v supply, 140ksps, 12-bit sampling a/d converter u a o pp l ic at i ty p i ca l
2 ltc1282 a u g w a w u w a r b s o lu t exi t i s (notes 1 and 2) supply voltage (v dd ) .............................................. 12v negative supply voltage (v ss )................... C 6v to gnd total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) .............................. v ss C 0.3v to v dd + 0.3v digital input voltage (note 4) ........... v ss C 0.3v to 12v digital output voltage (note 3) .............................. v ss C 0.3v to v dd + 0.3v power dissipation ............................................. 500mw specified temperature range (note 14) ..... 0 c to 70 c operating temperature range ltc1282ac, ltc1282bc ......................... 0 c to 70 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio t jmax = 110 c, q ja = 100 c/w (n) t jmax = 110 c, q ja = 130 c/w (sw) order part number ltc1282acn ltc1282bcn ltc1282acsw ltc1282bcsw consult factory for industrial and military grade parts. (note 14) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 10khz/70khz input signal 71/69 db thd total harmonic distortion 10khz/70khz input signal, up to 5th harmonic C 82/C 77 db peak harmonic or spurious noise 10khz/70khz input signal C 82/C 77 db imd intermodulation distortion f in1 = 19.0khz, f in2 = 20.6khz C 78 db full power bandwidth 4 mhz full linear bandwidth (s/(n + d) 3 68db) 200 khz with internal reference (notes 5 and 6) cc hara terist ics co u verter parameter conditions min typ max min typ max units resolution (no missing codes) l 12 12 bits integral linearity error (note 7) 1/2 1 lsb commercial l 1/2 1 lsb military l 3/4 1 lsb differential linearity error commercial l 3/4 1 lsb military l 1 1 lsb offset error (note 8) 3 4 lsb l 4 6 lsb gain error 10 15 lsb gain error tempco i out(ref) = 0 l 5 25 10 45 ppm/ c power supply rejection (note 9) v dd 10% 0.3 0.3 lsb (note 10) v ss 10% 0.1 0.1 lsb ltc1282a ltc1282b accuracy ic dy u w a ltc1282a/ltc1282b (note 5) 1 2 3 4 5 6 7 8 9 10 11 12 top view sw package 24-lead plastic so wide 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd v dd v ss busy cs rd hben nc nc d0/8 d1/9 d2/10 d3/11 n package 24-lead pdip
3 ltc1282 symbol parameter conditions min typ max units v in analog input range (note 11) 2.7v v dd 3.6v (unipolar mode) 0 to 2.5 v 3v v dd 3.6v, C 3.3v v ss C 2.5v (bipolar mode) 1.25 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions (sample mode) 63 pf during conversions (hold mode) 5 pf t acq sample-and-hold commercial l 0.45 1.14 m s acquisition time military l 1.5 m s (note 5) put u i a a u log ltc1282a/ltc1282b parameter conditions min typ max min typ max units v ref output voltage i out = 0 1.1900 1.200 1.210 1.190 1.200 1.210 v v ref output tempco i out = 0 l 5 25 10 45 ppm/ c v ref line regulation 2.7v v dd 3.6v 0.55 0.55 lsb/v C 3.6v v ss C 2.7v 0.02 0.02 lsb/v v ref load regulation 0v | i out | 1ma 3 3 lsb/ma ltc1282b ltc1282a i ter al refere ce characteristics (note 5) u uu symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.6v l 1.9 v v il low level input voltage v dd = 2.7v l 0.45 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 2.7v i o = C 10 m a 2.6 v i o = C 200 m a l 2.3 v v ol low level output voltage v dd = 2.7v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz high z output leakage d11-d0/8 v out = 0v to v dd , cs high l 10 m a c oz high z output capacitance d11-d0/8 cs high (note 12 ) l 15 pf i source output source current v out = 0v C 4.5 ma i sink output sink current v out = v dd 4.5 ma ltc1282a/ltc1282b (note 5) digital i puts a d digital outputs u u symbol parameter conditions min typ max units v dd positive supply voltage unipolar mode (note 13) 2.7 3.6 v bipolar mode (note 13) 3.0 3.6 v v ss negative supply voltage bipolar operation (note 13) C 3.6 C 2.5 v i dd positive supply current f sample = 140ksps l 4 7.8 ma i ss negative supply current f sample = 140ksps l 0.03 0.15 ma p d power dissipation f sample = 140ksps l 12 24 mw (note 5) ltc1282a/ltc1282b power require e ts w u
4 ltc1282 symbol parameter conditions min typ max units f sample(max) maximum sampling frequency commercial (note 13) l 140 khz military (note 13) l 120 khz t conv conversion time commercial l 6.0 m s military l 6.5 m s t 1 cs to rd setup time l 0ns t 2 rd to busy delay c l = 50pf 140 200 ns commercial l 230 ns military l 260 ns t 3 data access time after rd c l = 20pf (note 13) 100 180 ns commercial l 200 ns military l 220 ns c l = 100pf (note 13) 110 200 ns commercial l 240 ns military l 260 ns t 4 rd pulse width (note 13) l t 3 ns t 5 cs to rd hold time (note 13) l 0ns t 6 data setup time after busy - (note 13) 60 85 ns commercial l 110 ns military l 120 ns t 7 bus relinquish time (note 13) 40 60 120 ns commercial l 40 130 ns military l 40 150 ns t 8 hben to rd setup time (note 13) l 0ns t 9 hben to rd hold time (note 13) l 0ns t 10 delay between rd operations l 40 ns t 11 delay between conversions commercial (note 13) l 1140 450 ns military (note 13) l 1500 ns t 12 aperture delay of sample-and-hold 30 ns ti i g characteristics w u (note 5) ltc1282a/ltc1282b note 8: bipolar offset is the different voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: full-scale change when v ss = 0v (unipolar mode) or C 3v (bipolar mode). note 10: full-scale change when v dd = 3v. note 11: the ltc1282 can perform unipolar and bipolar conversions. when v ss is grounded (i.e. C 0.1v v ss ), the adc will convert in unipolar mode with input voltage of 0v to 2.5v. when v ss is taken negative (i.e. v ss C 2.5v), the adc will convert in bipolar mode with an input voltage of 1.25v. a in must not exceed v dd or fall below v ss by more than 50mv for specified accuracy. note 12: guaranteed by design, not subject to test. note 13: recommended operating conditions. note 14: commercial grade parts are designed to operate over the temperature range of C 40 c to 85 c but are neither tested nor guaranteed beyond 0 c to 70 c. industrial grade parts specified and tested over C40 c to 85 c are available on special request. consult factory. the l indicates specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 3v, v ss = 0v for unipolar mode and v ss = C 3v for bipolar mode, f sample = 140khz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for unipolar and bipolar modes. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band.
5 ltc1282 ti i g characteristics (note 5) w u slow memory mode, parallel read timing diagram rom mode, parallel read timing diagram slow memory mode, two byte read timing diagram busy data track old data db11 to db0 new data db11 to db0 t 1 hold ltc1282 ?tc01 cs rd t 5 t 1 t 10 t 11 t 2 t conv t 7 t 6 t 3 t 12 t 1 old data db11 to db0 new data db11 to db0 data track hold cs rd busy ltc1282 ?tc02 t 5 t 1 t 5 t 4 t 2 t conv t 11 t 2 t conv t 3 t 7 t 3 t 7 t 12 t 12 t 4 rom mode, two byte read timing diagram cs rd busy data track hold hben old data db7 to db0 new data db7 to db0 new data db11 to db8 ltc1282 ?tc03 t 7 t 8 t 1 t 2 t 3 t 12 t 6 t 7 t 3 t conv t 9 t 8 t 9 t 5 t 4 t 1 t 5 t 10 t 10 t 11 t 12 cs rd busy data track hold hben old data db7 to db0 new data db7 to db0 new data db11 to db8 ltc1282 ?tc04 t 8 t 9 t 8 t 9 t 8 t 9 t 1 t 4 t 5 t 1 t 4 t 5 t 1 t 5 t 4 t 2 t conv t 11 t 10 t 2 t 7 t 3 t 7 t 3 t 7 t 3 t 12 t 12
6 ltc1282 cc hara terist ics uw a t y p i ca lper f o r c e power supply feedthrough vs ripple frequency distortion vs input frequency (unipolar) integral nonlinearity intermodulation distortion plot differential nonlinearity code 0 ? differential nonlinearity error (lsbs) 0.5 0 0.5 1 512 1024 1536 2048 ltc1282 ?tpc02 2560 3072 3584 4096 supply voltage (v) 2.5 supply current (ma) 12 16 20 4.5 ltc1282 ?tpc04 8 4 0 3 3.5 4 5 10 14 18 6 2 single supply dual supplies f sample = 160khz t a = 25? input frequency (hz) ?0 amplitude (db below the fundamental) ?0 ?0 ?0 0 1k 100k 1m 10m ltc1282 ?tpc06 100 10k ?0 ?0 ?0 ?0 ?0 f sample = 160khz 3v supply unipolar 3rd harmonic thd 2nd harmonic input frequency (hz) 2 effective number of bits (enobs) 4 6 8 10 1k 100k 1m 10m ltc1282 ?tpc05 0 10k 12 1 3 5 7 9 11 50 62 74 56 68 s/(n + d) (db) f sample = 160khz v s = 2.7v bipolar v s = 3v unipolar bipolar (1.25v input) unipolar (0v ?2.5v input) enobs and s/(n + d) vs input frequency distortion vs input frequency (bipolar) input frequency (hz) ?0 amplitude (db below the fundamental) ?0 ?0 ?0 0 1k 100k 1m 10m ltc1282 ?tpc07 100 10k ?0 ?0 ?0 ?0 ?0 2nd harmonic thd f sample = 140khz 3v supplies bipolar 3rd harmonic ripple frequency (hz) 1k ?0 amplitude of power supply feedthrough (db) ?0 ?0 ?0 ?0 10k 100k 1m ltc1282 ?tpc08 ?0 ?0 ?0 100 ?0 0 f sample = 140khz v dd (v ripple = 2.5mv) v ss (v ripple = 2.5mv) dgnd (v ripple = 250mv) code 0 ? integral nonlinearity error (lsbs) 0.5 0 0.5 1 512 1024 1536 2048 ltc1282 ?tpc01 2560 3072 3584 4096 supply current (i dd ) vs temperature temperature (?) ?0 0 supply current (ma) 1 3 4 5 10 7 0 50 75 ltc1282 ?tpc03 2 8 9 6 ?5 25 100 125 f sample = 160khz v dd = 3v supply current (i dd ) vs supply voltage frequency (hz) 0 120 amplitude (db) 100 ?0 ?0 ?0 20k 40k 60k 80k ltc1282 ?tpc09 ?0 0 10k 30k 50k 70k f sample = 160khz f in1 = 19.0khz f in2 = 20.6khz v dd = 3v unipolar
7 ltc1282 s/(n + d) vs input frequency and amplitude (unipolar, v dd = 3v) s/(n + d) vs input frequency and amplitude (bipolar, 3v supplies) cc hara terist ics uw a t y p i ca lper f o r c e input frequency (hz) 20 signal/(noise + distortion) (db) 40 50 70 80 1k 100k 1m 10m ltc1282 ?tpc10 0 10k 60 30 10 f sample = 160khz unipolar v in = 60db v in = 20db v in = 0db input frequency (hz) 20 signal/(noise + distortion) (db) 40 50 70 80 1k 100k 1m 10m ltc1282 ?tpc10 0 10k 60 30 10 f sample = 160khz v in = 60db v in = 20db v in = 0db input frequency (hz) ?0 amplitude (db) ?0 ?0 ?0 0 100 10k 100k 1m ltc1282 ?tpc12 100 1k ?0 ?0 ?0 ?0 ?0 f sample = 160khz v dd = 3v unipolar spurious free dynamic range vs input frequency reference voltage vs load current s/(n +d) vs input frequency vs source resistance (bipolar) load current (ma) ? reference voltage (v) 1.200 1.210 1.220 ? ltc1282 ?tpc13 1.190 1.180 1.170 ? ? ? 0 1 1.195 1.205 1.215 1.185 1.175 v dd = 3v input frequency (hz) 20 signal/(noise + distortion) (db) 40 50 70 80 1k 100k 1m 10m ltc1282 ?tpc14 0 10k 60 30 10 v dd = 3v v ss = 3v bipolar r s = 50 w r s = 500 w r s = 1k r s = 5k temperature (?) ?0 0 magnitude of offset voltage change (lsbs) 2 5 0 50 75 ltc1282 ?tpc15 1 4 3 ?5 25 100 125 f sample = 140khz v dd = 2.7v temperature (?) ?0 0 magnitude of gain error change (lsbs) 2 5 0 50 75 ltc1282 ?tpc16 1 4 3 ?5 25 100 125 f sample = 140khz v dd = 2.7v change in integral nonlinearity (inl) vs temperature temperature (?) ?0 0 magnitude of integral nonlinearity change (lsbs) 0.2 0.5 0 50 75 ltc1282 ?tpc17 0.1 0.4 0.3 ?5 25 100 125 f sample = 140khz v dd = 2.7v change in differential nonlinearity (dnl) vs temperature temperature (?) ?0 0 magnitude of differential nonlinearity change (lsbs) 0.2 0.5 0 50 75 ltc1282 ?tpc18 0.1 0.4 0.3 ?5 25 100 125 f sample = 140khz v dd = 2.7v change in offset voltage vs temperature change in gain error vs temperature
8 ltc1282 change in offset voltage vs supply voltage change in gain error vs supply voltage change in integral nonlinearity (inl) vs supply current change in differential nonlinearity (dnl) vs supply current supply voltage (v) 2 0 magnitude of integral nonlinearity change (lsbs) 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 ltc1282 ?tpc21 4.5 5 f sample = 140khz supply voltage (v) 2 0 magnitude of differential nonlinearity change (lsbs) 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 ltc1282 ?tpc22 4.5 5 f sample = 140khz cc hara terist ics uw a t y p i ca lper f o r c e supply voltage (v) 2 0 magnitude of offset voltage change (lsbs) 0.2 0.3 0.4 0.5 0.6 0.7 2.5 3 3.5 4 ltc1282 ?tpc19 4.5 0.8 0.9 1 0.1 5 f sample = 140khz supply voltage (v) 2 0 magnitude of gain error change (lsbs) 1 2 3 4 5 2.5 3 3.5 4 ltc1282 ?tpc20 4.5 5 f sample = 140khz
9 ltc1282 pi fu ctio s uu u a in (pin 1): analog input. 0v to 2.5v (unipolar), 1.25v (bipolar). v ref (pin 2): +1.20v reference output. bypass to agnd (10 m f tantalum in parallel with 0.1 m f ceramic). agnd (pin 3): analog ground. d11-d4 (pins 4 to 11): three-state data outputs. d11 is the most significant bit. dgnd (pin 12): digital ground. d3/11-d0/8 (pins 13 to 16): three-state data outputs. nc (pins 17 and 18): no connection. hben (pin 19): high byte enable input. this pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (d7 and d0/8). see table 1. hben also disables conversion start when high. rd (pin 20): read input. this active low signal starts a conversion when cs and hben are low. rd also enables the output drivers when cs is low. cs (pin 21): the chip select input must be low for the adc to recognize rd and hben inputs. busy (pin 22): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 23): bipolar mode negative supply, C 3v. bypass to agnd with 0.1 m f ceramic. unipolar mode tie to dgnd. v dd (pin 24): positive supply, 3v. bypass to agnd (10 m f tantalum in parallel with 0.1 m f ceramic). table 1. data bus output, cs and rd = low pin 4 pin 5 pin 6 pin 7 pin 8 pin 9 pin 10 pin 11 pin 13 pin 14 pin 15 pin 16 mnemonic* d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 hben = low db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 hben = high db11 db10 db9 db8 low low low low db11 db10 db9 db8 *d11...d0/8 are the adc data output pins. db11...db0 are the 12-bit conversion results, db11 is the msb. test circuits load circuits for access time load circuits for output float delay 3k c l c l dbn (a) hi-z to v oh , (t 3 ) and v ol to v oh , (t 6 ) (b) hi-z to v ol , (t 3 ) and v oh to v ol , (t 6 ) dbn 3k 5v 1282 tc01 dgnd dgnd 3k 10pf 10pf dbn (a) v oh to hi-z (b) v ol to hi-z dbn 3k 5v 1282 tc02 dgnd dgnd
10 ltc1282 fu tio al block diagra uu w u s a o pp l ic at i wu u i for atio conversion details the ltc1282 uses a successive approximation and an internal sample-and-hold circuitry to convert an analog signal to a 12-bit parallel or 2-byte output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. please refer to the digital interface section for the data format. conversion start is controlled by the cs, rd and hben inputs. at the start of conversion the successive approxi- mation register (sar) is reset and the three-state data outputs are enabled. once a conversion cycle has begun it cannot be restarted. during conversion, the internal 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in input connects to the sample-and-hold capacitor during the sample phase, and the comparator offset is nulled by the feedback switch. in this sample phase, a minimum delay of 1.14 m s will provide enough time for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. the input switch switches c sample to ground, injecting the analog input charge to the summing junction. this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the a in input charge. the sar contents (a 12-bit data word) which represent the a in are loaded into the 12-bit latch. v dac ltc1282 ?f01 + c dac dac sample hold c sample s a r 12-bit latch comparator sample si a in figure 1. a in input c sample control logic internal clock successive approximation register 12 12 output latches ? ? d11 d0/8 busy 1.2v reference v ref(out) dgnd agnd a in sample hold sample v ss (3v for bipolar mode, agnd for unipolar mode) v dd hben cs rd ltc1282 ?fbd 12-bit capacitive dac comparator +
11 ltc1282 u s a o pp l ic at i wu u i for atio dynamic performance the ltc1282 has exceptionally high speed sampling capa- bility. fft (fast fourier transform) test techniques are used to characterize the adcs frequency response, distor- tion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1282 fft plot. signal-to-(noise + distortion) ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical ltc1282 fft plot. figure 2. ltc1282 nonaveraged, 1024 point fft plot input frequency (hz) 2 effective number of bits (enobs) 4 6 8 10 1k 100k 1m 10m ltc1282 ?f03 0 10k 12 1 3 5 7 9 11 50 62 74 56 68 s/(n + d) (db) f sample = 160khz v s = 2.7v bipolar bipolar (1.25v input) total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ? v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. the typical thd specifi- cation in the dynamic accuracy table includes the 2nd through 5th harmonics. with a 70khz input signal, the ltc1282 has a typical C 82db thd as shown in figure 4. figure 3. enobs and s/(n + d) vs input frequency input frequency (hz) ?0 amplitude (db below the fundamental) ?0 ?0 ?0 0 1k 100k 1m 10m ltc1282 ?f04 100 10k ?0 ?0 ?0 ?0 ?0 2nd harmonic thd f sample = 140khz 3v supplies bipolar 3rd harmonic figure 4. distortion vs input frequency (bipolar) effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 140khz the ltc1282 maintains 11.3 enobs at 70khz input frequency. refer to figure 3. frequency (khz) 0 amplitude (db) 20 40 60 80 lt1282 ?f02 0 20 40 60 80 100 120 10 30 50 70 f sample = 160khz v dd = 3v unipolar
12 ltc1282 u s a o pp l ic at i wu u i for atio intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb) and (fa C fb) while the 3rd order imd terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb) if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order. imd products can be expressed by the follow- ing formula: imd (fa ?fb) = 20log amplitude at (fa ?fb) amplitude at fa figure 5 shows the imd performance at a 20khz input. frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 20 40 60 80 ltc1282 ?f05 ?0 0 10 30 50 70 f sample = 160khz f in1 = 19.0khz f in2 = 20.6khz v dd = 3v unipolar figure 5. intermodulation distortion plot full power and full linear bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1282 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. driving the analog input the analog input of the ltc1282 is easy to drive. it draws only one small current spike while charging the sample- and-hold capacitor at the end of conversion. during con- version the analog input draws no current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. any op amp that settles in 1.14 m s to small current transients will allow maximum speed opera- tion. if slower op amps are used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adcs a in input include the lt ? 1190/lt1191, lt1007, lt1220, lt1223 and lt1224 op amps. the analog input tolerates source resistance very well. here again, the only requirement is that the analog input must settle before the next conversion starts. for larger source resistance, full accuracy can be obtained if more time is allowed between conversions. internal reference the ltc1282 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 1.20v. it is internally connected to the dac and is available at pin 2 to provide up to 0.3ma current to an external load. for minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 m f tantalum in parallel with a 0.1 m f ceramic). peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal.
13 ltc1282 u s a o pp l ic at i wu u i for atio overdriving the internal reference the v ref pin can be driven above its normal value with a dac or other means to provide input span adjustment. figure 6 shows an lt1006 op amp driving the reference pin. the v ref pin must be driven to at least 1.25v to prevent conflict with the internal reference. the reference should be driven to no more than 1.44v in unipolar mode or 2.88v for bipolar mode to keep the input span within the single 3v or 3v supplies. figure 6. driving the v ref with the lt1006 op amp natural binary with 1lsb = fs/4096 = 2.5v/4096 = 0.61mv. figure 9 shows the input/output transfer characteristics for the ltc1282 in bipolar operation. the full scale for ltc1282 in bipolar mode is still 2.5v and 1lsb = 0.61mv. unipolar/bipolar operation and adjustment figure 8 shows the ideal input/output characteristics for the ltc1282. the code transitions occur midway be- tween successive integer lsb values (i.e., 0.5lsb, 1.5lsbs, 2.5lsbs, fs C 1.5lsbs). the output code is figure 7. supplying a 2.5v reference voltage to the ltc1282 with the lt1019a-2.5 figure 7 shows a typical reference, the lt1019a-2.5 connected to the ltc1282 operating in bipolar mode. this will provide an improved drift (due to the 5ppm/ c of the lt1019a-2.5) and a 2.604v full scale. input voltage (v) 0v output code fs ?1lsb ltc1282 ?f8 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs/4096 fs = 2.5v figure 8. ltc1282 unipolar transfer characteristic figure 9. ltc1282 bipolar transfer characteristic unipolar offset and full-scale adjustment in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. figure 10 shows the extra components required for full-scale error adjustment. if both offset and full-scale adjust- ments are needed, the circuit in figure 11 can be used. offset should be adjusted before full scale. to adjust input voltage (v) 0v output code ? lsb ltc1282 ?f09 011...111 011...110 000...001 000...000 100...000 100...001 100...010 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 2.5v 1lsb = fs/4096 111...110 v ref(out) 3 1.25v 3 w input range 1.033v ref(out) + lt1006 10 m f ltc1282 ?f06 ltc1282 a in agnd v ref v dd v ss 3v ?v 3 w input range 2.60v ltc1282 a in agnd v ref 10 m f ltc1282 ?f07 lt1019a-2.5 v in gnd v out 5v v dd v ss 3v ?v +
14 ltc1282 u s a o pp l ic at i wu u i for atio offset, apply 0.305mv (i.e., 0.5lsb) at v1 and adjust the op amp offset voltage until the ltc1282 output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error, apply an analog input of 2.49909v (i.e., fs C 1.5 lsbs or last code transition) at the input and adjust the full-scale trim until the ltc1282 output code flickers between 1111 1111 1110 and 1111 1111 1111. figure 10. full-scale adjust circuit figure 11. unipolar offset and full-scale adjust circuit figure 12. bipolar offset and full-scale adjust circuit error adjustment is achieved by trimming the offset ad- justment of figure 12 while the input voltage is 0.5lsb below ground. this is done by applying an input voltage of C 0.305mv (C 0.5lsb for ltc1282) to the input in figure 12 and adjusting r8 until the adc output code flickers between 0000 0000 0000 and 1111 1111 1111. for full- scale adjustment, an input voltage of 1.24909v (fs C 1.5lsbs for ltc1282) is applied to the input and r5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. board layout and bypassing the ltc1282 is easy to use. to obtain the best perfor- mance from the device, a printed circuit board is recom- mended. layout for the printed circuit board should en- sure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in figure 13. in bipolar mode, a 0.1 m f ceramic provides adequate bypassing for the v ss pin. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. bipolar offset and full-scale adjustment bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. figure 10 shows the extra components required for full-scale error adjust- ment. if both offset and full-scale adjustments are needed, the circuit in figure 12 can be used. again, bipolar offset must be adjusted before full-scale error. bipolar offset ltc1282 a in agnd ltc1282 ?f10 r4 100 w full-scale adjust r5 10k r2 10k r1 50 w v 1 + a1 additional pins omitted for clarity 20lsb trim range a in ltc1282 ?f11 r2 10k r4 100k r1 10k 10k 5v r9 20 w analog input 0v to 2.5v r3 100k 5v r8 10k offset adjust r6 400 w r5 4.3k full-scale adjust r7 100k + ltc1282 a in ltc1282 ?f12 r2 10k r4 100k r1 10k analog input 1.25v r3 100k 5v r8 20k offset adjust r6 200 w r5 4.3k full-scale adjust r7 100k + ltc1282 ?v
15 ltc1282 u s a o pp l ic at i wu u i for atio ltc1282 ?f13 a in agnd v ref v dd dgnd ltc1282 digital system 0.1 m f + analog ground plane ground connection to digital circuitry analog input circuitry 3 2 24 12 1 0.1 m f 10 m f 10 m f figure 13. power supply grounding practice noise: input signal leads to a in and signal return leads from agnd (pin 3) should be kept as short as possible to minimize input noise coupling. in applications where this is not possible, a shielded cable between source and adc is recommended. also, since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit imped- ances as much as possible. a single point analog ground separate from the logic system ground should be established with an analog ground plane at pin 3 (agnd) or as close as possible to the adc, as shown in figure 13. pin 12 ( dgnd) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be con- nected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. digital interface the adc is designed to interface with microprocessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. the hben input serves as a data byte select for 8-bit proces- sors and is normally either connected to the microproces- sor address bus or grounded. connecting to 5v logic systems the ltc1282 interfaces well to 5v logic because the esd clamps on the inputs do not clamp to the positive supply (see figure 14). inputs of 0v to 5v do not bother the adc at all. in addition, the 0v to 3v outputs of the 3v adc are more than adequate to meet ttl input levels in the 5v logic. (5v logic with cmos input levels requires a level shift.) figure 14. 3v adc esd protection handles 0v to 5v swings easily ltc1282 3v adc 3v ltc1282 ?f14 adc outputs 0v to 3v 5v adc inputs 0v to 5v ttl input levels cmos output levels 5v logic ltc esd clamp
16 ltc1282 u s a o pp l ic at i wu u i for atio internal clock the ltc1282 has an internal clock that eliminates the need for synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 5.5 m s, and a maximum conversion time over the full operating temperature range of 6.0 m s. no external adjust- ments are required and, with the guaranteed maximum acquisition time of 1.14 m s, throughput performance of 140ksps is assured. timing and control conversion start and data read operations are controlled by three digital inputs: hben, cs and rd. figure 15 shows the logic structure associated with these inputs. the three signals are internally gated so that a logic 0 is required on all three inputs to initiate a conversion. once initiated it cannot be restarted until the conversion is complete. converter status is indicated by the busy output, and this is low while conversion is in progress. initiates a conversion and data is read when conversion is complete. the second is the rom mode which does not require microprocessor wait states. a read operation brings cs and rd low which initiates a conversion and reads the previous conversion result. data format the output format can be either a complete parallel load for 16-bit microprocessors or a two byte load for 8-bit micro- processors. data is always right justified (i.e., lsb is the most right-hand bit in a 16-bit word). for a two byte read, only data outputs d7...d0/8 are used. byte selection is governed by the hben input which controls an internal digital multiplexer. this multiplexes the 12-bits of conver- sion data onto the lower d7...d0/8 outputs (4msbs or 8msbs) where it can be read in two read cycles. the 4msbs always appear on d11...d8 whenever the three- state output drivers are turned on. slow memory mode, parallel read (hben = low) figure 16 and table 2 show the timing diagram and data bus status for slow memory mode, parallel read. cs and rd going low trigger a conversion and the adc acknowl- edges by taking busy low. data from the previous conver- sion appears on the three-state data outputs. busy re- turns high at the end of conversion when the output latches have been updated and the conversion result is placed on data outputs d11...d0/8. slow memory mode, two byte read for a two byte read, only 8 data outputs d7...d0/8 are used. conversion start procedure and data output status for the first read operation are identical to slow memory mode, parallel read. see figure 17 timing diagram and table 3 data bus status. at the end of the conversion, the low data byte (d7...d0/8) is read from the adc. a second read operation with the hben high, places the high byte on data outputs d3/11...d0/8 and disables conversion start. note the 4msbs appear on data output d11...d8 during the two read operations. figure 15. internal logic for control inputs cs, rd and hben there are two modes of operation as outlined by the timing diagrams of figures 16 to 19. slow memory mode is designed for microprocessors which can be driven into a wait state. a read operation brings cs and rd low which conversion start (rising edge trigger) ltc1282 ?f15 busy flip flop clear q d 19 21 20 active high active high enable three-state outputs d11....d0/8 = db11....db0 enable three-state outputs d11....d8 = db11....db8 d7....d4 = low d3/11....d0/8 = db11....db8 hben cs rd ltc1282 d11....d0/8 are the adc data output pins db11....db0 are the 12-bit conversion results *
17 ltc1282 u s a o pp l ic at i wu u i for atio table 2. slow memory mode, parallel read data bus status data outputs d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 read db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 figure 16. slow memory mode, parallel read timing diagram t 1 t 2 t 11 t 10 t 6 t 7 t 5 t 1 t 3 t 12 t conv old data db11-db0 new data db11-db0 track hold data busy rd cs rd ltc1282 ?f16 table 3. slow memory mode, two byte read data bus status data outputs d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read db7 db6 db5 db4 db3 db2 db1 db0 second read low low low low db11 db10 db9 db8 old data db7-db0 new data db7-db0 track hold data busy rd cs rd ltc1282 ?f17 t 8 t 1 t 2 t 3 t conv t 11 t 9 t 8 t 9 t 5 t 1 t 4 t 5 t 10 t 10 t 6 t 7 t 3 t 7 t 12 t 12 hben new data db11-db8 figure 17. slow memory mode, two byte read timing diagram
18 ltc1282 u s a o pp l ic at i wu u i for atio table 4. rom mode, parallel read data bus status data outputs d11 d10 d9 d8 d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read (old data) db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 second read db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 figure 18. rom mode, parallel read timing diagram (hben = low) hold t 12 t 7 track data t 3 t 7 t 3 t 2 t conv t conv t 11 t 1 t 4 t 5 t 4 t 1 t 5 t 2 t 12 old data db11-db0 new data db11-db0 busy rd cs ltc1282 ?f18 rom mode, parallel read (hben = low) the rom mode avoids placing a microprocessor into a wait state. a conversion is started with a read operation, and the 12 bits of data from the previous conversion are available on data outputs d11...d0/8 (see figure 18 and table 4). this data may be disregarded if not required. a second read operation reads the new data (db11...db0) and starts another conversion. a delay at least as long as the adcs conversion time plus the 1.0 m s minimum delay between conversions must be allowed between read operations. rom mode, two byte read as previously mentioned for a two byte read, only data outputs d7...d0/8 are used. conversion is started in the normal way with a read operation and the data output status is the same as the rom mode, parallel read (see figure 19 timing diagram and table 5 data bus status). two more read operations are required to access the new conversion result. a delay equal to the adcs conversion time must be allowed between conversion start and the second data read operation. the second read operation with hben high disables conversion start and places the high byte (4msbs) on data outputs d3/11...d0/8. a third read operation accesses the low data byte (db7...db0) and starts another conversion. the 4msbs appear on data outputs d11...d8 during all three read operations. microprocessor interfacing the ltc1282 allows easy interfacing to digital signal processors as well as modern high speed, 8-bit or 16- bit microprocessors. here are several examples. tms320c25 figure 20 shows an interface between the ltc1282 and the tms320c25. the r/w signal of the dsp initiates a conversion and conversion results are read from the ltc1282 using the following instruction: in d, pa
19 ltc1282 u s a o pp l ic at i wu u i for atio figure 19. rom mode two byte read timing diagram table 5. rom mode, two byte read data bus status data outputs d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 first read (old data) db7 db6 db5 db4 db3 db2 db1 db0 second read (new data) low low low low db11 db10 db9 db8 third read (new data) db7 db6 db5 db4 db3 db2 db1 db0 old data db7-db0 new data db11-db8 track hold data busy rd cs rd ltc1282 ?f19 t 8 t 1 t 2 t 3 t conv t 11 t 9 t 8 t 9 t 5 t 1 t 4 t 5 t 10 t 3 t 7 t 3 t 7 t 12 t 12 hben t 7 t 4 t 1 t 8 t 9 new data db7-db0 t 2 t 4 t 5 where d is data memory address and pa is the port address. mc68000 microprocessor figure 21 shows a typical interface for the mc68000. the ltc1282 is operating in the slow memory mode. assum- ing the ltc1282 is located at address c000, then the following single 16-bit move instruction both starts a conversion and reads the conversion result: move.w $c000,d0 at the beginning of the instruction cycle when the adc address is selected, busy and cs assert dtack so that the mc68000 is forced into a wait state. at the end of conversion, busy returns high and the conversion result is placed in the d0 register of the microprocessor. figure 20. tms320c25 interface data bus ltc1282 ?f20 address bus d0 d16 r/w ready is a1 a16 tms320c25 address decode en d0/8 d11 rd busy cs hben ltc1282 additional pins omitted for clarity
20 ltc1282 u s a o pp l ic at i wu u i for atio this is a two byte read instruction which loads the adc data (address b000) into the hl register pair. during the first read operation, busy forces the microprocessor to wait for the ltc1282 conversion. no wait states are inserted during the second read operation when the mi- croprocessor is reading the high data byte. tms32010 microcomputer figure 23 shows an ltc1282/tms32010 interface. the ltc1282 is operating in the rom mode. the interface is designed for a maximum tms32010 clock frequency of 18mhz but will typically work over the full tms32010 clock frequency range. the ltc1282 is mapped at a port address. the following i/o instruction starts a conversion and reads the previous conversion result into data memory. in a,pa (pa = port address) when conversion is complete, a second i/o instruction reads the up-to-date data into memory and starts another conversion. a delay at least as long as the adc conversion time must be allowed between i/o instructions. data bus ltc1282 ?f21 address bus d0 d11 r/w dtack as a1 a23 mc68000 address decode en d0/8 d11 rd busy cs hben ltc1282 additional pins omitted for clarity figure 21. mc68000 interface 8085a/z80 microprocessor figure 22 shows an ltc1282 interface for the z80 and 8085a. the ltc1282 is operating in the slow memory mode and a two byte read is required. not shown in the figure is the 8-bit latch required to demultiplex the 8085a common address/data bus. a0 is used to assert hben so that an even address (hben = low) to the ltc1282 will start a conversion and read the low data byte. an odd address (hben = high) will read the high data byte. this is accomplished with the single 16-bit load instruction below. for the 8085a lhld (b000) for the z80 ldhl, (b000) figure 22. 8085a and z80 interface data bus ltc1282 ?f23 port address bus d0 d11 den pa0 pa2 tms32010 address decode en d0/8 d11 rd cs hben ltc1282 linear circuitry omitted for clarity figure 23. tms32010 interface data bus ltc1282 ?f22 address bus d0 d7 rd wait mreq a0 a15 z80 8085a address decode en d0/8 d7 rd busy cs hben linear circuitry omitted for clarity ltc1282 a0
21 ltc1282 u s a o pp l ic at i wu u i for atio figure 25. d time measurement with the ltc1282 muxing with cd4051 the high input impedance of the ltc1282 provides an easy, cheap, fast, and accurate way to multiplex many channels of data through one converter. figure 24 shows a low cost cd4051, one of the most common multiplex- ers connected to the ltc1282. the ltc1282s input draws no dc input current so it can be accurately driven by the unbuffered mux. the cd4520 counter increments the mux channel after each sample is taken. 100ps resolution d time measurement with ltc1282 figure 25 shows a circuit that precisely measures the difference in time between two events. it has a 400ns full scale and 100ps resolution. the start signal releases the ramp generator made up of the pnp current source and the 500pf capacitor. the circuit ramps until the stop signal shuts off the current source. the final value of the ramp represents the time between the start and stop events. the ltc1282 digitizes this final value and out- puts the digital data. figure 24. muxing the ltc1282 with cd4051 v ss gnd a in ref out v dd ltc1282 cs rd busy 12-bit data output 10 m f 2n2369 2n2369 20k 200k 250pf polystyrene 430 w 2n5771 65 w 3.3v 74hc03 65 w 45.3 w 45.3 w 1n457 lm134 d clk q q clr d clk q q clr 1k 5v 5v start - 5v stop - data latch signal 10 m f 1k 5v 100k 1n4148 0.001 m f 10k 1n457 74hc74 10pf 1k 1n4148 100pf 10k ltc1282 ?f25 v ss abc 8 input channels 1.25v input varies no buffer required d11 d0 ? ? cs rd busy ltc1282 a in m p or dsp enable reset q2 q1 q0 cd4520 counter ltc1282 ?f24 3v ?v cd4051
22 ltc1282 u s a o pp l ic at i wu u i for atio other high speed a/d converters ltc makes a family of high speed sampling adcs for a variety of applications. both single 5v and 5v supply devices are available at high speeds. the high speed 12-bit family is summarized below. *6mw power shutdown with instant wake up ltc1273/5/6 a in v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd v dd nc busy cs rd hben d0/8 d1/9 d2/10 d3/11 + 10 m f 0.1 m f analog input 2.42v v ref output 8- or 12-bit parallel bus m p control lines + 0.1 m f 10 m f 5v 2.7 m s conversion time built-in sample & hold reference output for system use parallel outputs for the fastest data transfer rates no negative supply required for unipolar operation internal clock no crystal required only 75mw power consumption reference on board 300ksps and 500ksps 12-bit sampling a/d converters comparison of specifications and features device sampling s/(n + d) input power power type freq @ nyquist range supply dissipation ltc1272 250khz 65db 0v-5v 5v 75mw ltc1273 300khz 70db 0v-5v 5v 75mw ltc1275 300khz 70db 2.5v 5v 75mw ltc1276 300khz 70db 5v 5v 75mw ltc1278 500khz 70db 0v-5v 5v 75mw or 2.5v or 5v 6mw* ltc1282 140khz 68db 0v-2.5v 3v 12mw or 1.25v or 3v
23 ltc1282 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. n package 24-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sw package 24-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s24 (wide) 0996 note 1 0.598 ?0.614* (15.190 ?15.600) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** n24 1197 0.255 0.015* (6.477 0.381) 1.265* (32.131) max 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
24 ltc1282 ? linear technology corporation 1993 lt/tp 1098 2k rev a ? printed in usa part number resolution speed comments 16-bit ltc1604 16 333ksps 2.5v input range, 5v supply ltc1605 16 100ksps 10v input range, single 5v supply 14-bit ltc1419 14 800ksps 150mw, 81.5db sinad and 95db sfdr ltc1416 14 400ksps 75mw, low power with excellent ac specs ltc1418 14 200ksps 15mw, single 5v, serial/parallel i/o 12-bit ltc1410 12 1.25msps 150mw, 71.5db sinad and 84db thd ltc1415 12 1.25msps 55mw, single 5v supply ltc1409 12 800ksps 80mw, 71.5db sinad and 84db thd ltc1279 12 600ksps 60mw, single 5v or 5v supply ltc1404 12 600ksps high speed serial i/o in so-8 package ltc1278-5 12 500ksps 75mw, single 5v or 5v supply ltc1278-4 12 400ksps 75mw, single 5v or 5v supply ltc1400 12 400ksps high speed serial i/o in so-8 package related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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